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ltc2356-12/ltc2356-14 1 2356fb block diagram features applications description serial 12-bit/14-bit, 3.5msps sampling adcs with shutdown the ltc ? 2356-12/ltc2356-14 are 12-bit/14-bit, 3.5msps serial adcs with differential inputs. the devices draw only 5.5ma from a single 3.3v supply and come in a tiny 10-lead msop package. a sleep shutdown feature further reduces power consumption to 13w. the com - bination of speed, low power and tiny package makes the ltc2356-12/ltc2356-14 suitable for high speed, portable applications. the 80db common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. the devices convert C1.25v to 1.25v bipolar inputs differentially. the absolute voltage swing for a in + and a in C extends from ground to the supply voltage. the serial interface sends out the conversion results during the 16 clock cycles following a conv rising edge for com - patibility with standard serial interfaces. if two additional clock cycles for acquisition time are allowed after the data stream in between conversions, the full sampling rate of 3.5msps can be achieved with a 63mhz clock. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. n 3.5msps conversion rate n 74.1db sinad at 14-bits, 71.1db sinad at 12-bits n low power dissipation: 18mw n 3.3v single supply operation n 2.5v internal bandgap reference can be overdriven n 3-wire spi-compatible serial interface n sleep (13w) shutdown mode n nap (4mw) shutdown mode n 80db common mode rejection n 1.25v bipolar input range n tiny 10-lead msop package n communications n data acquisition systems n uninterrupted power supplies n multiphase motor control n multiplexed data acquisition n rfid thd, 2nd and 3rd vs input frequency for differential input signals 2356 bd ? + 1 2 7 3 4 s & h gnd exposed pad ltc2356-14 v ref 10f a in ? a in + 14-bit adc 3.3v10f 14 14-bit latch 8 10 9 three- state serial output port 2.5v reference timing logic v dd sdo conv sck 5 6 11 frequency (mhz) 0.1 ?80 thd, 2nd, 3rd (db) ?74 ?68 ?62 ?56 1 10 100 2356 g02 ?86 ?92 ?98 ?104 ?50 thd 2nd 3rd
ltc2356-12/ltc2356-14 2 2356fb (notes 1, 2) supply voltage (v dd ) .................................................. 4v analog and v ref input voltages (note 3) .................................... C0.3v to (v dd + 0.3v ) digital input voltages ................... C 0.3v to (v dd + 0.3v ) digital output voltage ................... C 0.3v to (v dd + 0.3v ) power dissipation ............................................... 100mw operation temperature range ltc2356c-12/ltc2356c-14 ..................... 0c to 70c ltc2356i-12 / ltc2356i-14 ................... C 40c to 85c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) ................... 300c absolute maximum ratings absolute maximum ratings converter characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. with internal reference. v dd = 3.3v. parameter conditions ltc2356-12 ltc2356-14 units min typ max min typ max resolution (no missing codes) l 12 14 bits integral linearity error (notes 4, 5, 18) l C2 0.25 2 C4 0.5 4 lsb offset error (notes 4, 18) l C10 1 10 C30 2 30 lsb gain error (note 4, 18) l C40 5 40 C80 10 80 lsb gain tempco internal reference (note 4) external reference 15 1 15 1 ppm/c ppm/c order information lead free finish tape and reel part marking* package description temperature range ltc2356cmse-12 #pbf ltc2356cmse-12 #trpbf ltcwn 10-lead plastic msop 0c to 70c ltc2356imse-12 #pbf ltc2356imse-12 #trpbf ltcwn 10-lead plastic msop C40c to 85c ltc2356cmse-14 #pbf ltc2356cmse-14 #trpbf ltcvf 10-lead plastic msop 0c to 70c ltc2356imse-14 #pbf ltc2356imse-14 #trpbf ltcvf 10-lead plastic msop C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ pin configuration 1 2 3 4 5 a in + a in ? v ref gnd gnd 10 9 8 7 6 conv sck sdo v dd gnd top view 11 mse package 10-lead plastic msop t jmax = 125c, ja = 40c/w exposed pad (pin 11) is gnd, must be soldered to pcb
ltc2356-12/ltc2356-14 3 2356fb dynamic accuracy the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c with external reference = 2.55v. v dd = 3.3v. single-ended a in + signal drive with a in C = 1.5v dc. differential signal drive with v cm = 1.5v at a in + and a in C analog input the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. with internal reference. v dd = 3.3v. symbol parameter conditions min typ max units v in analog differential input range (notes 3, 8, 9) 3.1v v dd 3.6v l C1.25 to 1.25 v v cm analog common mode + differential input range (note 10) 0 to v dd v i in analog input leakage current l 1 a c in analog input capacitance (note 19) 13 pf t acq sample-and-hold acquisition time (note 6) l 39 ns t ap sample-and-hold aperture delay time 1 ns t jitter sample-and-hold aperture delay time jitter 0.3 ps cmrr analog input common mode rejection ratio f in = 1mhz, v in = 0v to 3v f in = 100mhz, v in = 0v to 3v C60 C15 db db symbol parameter conditions ltc2356-12 ltc2356-14 units min typ max min typ max sinad signal-to-noise plus distortion ratio 100khz input signal (note 19) 1.4mhz input signal (note 19) l 68 71.1 71.1 70 74.1 72.3 db db thd total harmonic distortion 100khz first 5 harmonics (note 19) 1.4mhz first 5 harmonics (note 19) l C86 C82 C76 C86 C82 C78 db db sfdr spurious free dynamic range 100khz input signal (note 19) 1.4mhz input signal (note 19) 86 82 86 82 db db imd intermodulation distortion 0.625v p-p to 1.4mhz summed with 0.625v p-p 1.56mhz into a in + and inverted into a in C C82 C82 db code-to-code transition noise v ref = 2.5v (note 18) 0.25 1 lsb rms full power bandwidth v in = 2.5v p-p , sdo = 11585lsb p-p (note 15) 50 50 mhz full linear bandwidth s/(n + d) 68db 5 5 mhz parameter conditions min typ max units v ref output voltage i out = 0 2.5 v v ref output tempco 15 ppm/c v ref line regulation v dd = 3.1v to 3.6v, v ref = 2.5v 600 v/v v ref output resistance load current = 0.5ma 0.2 v ref settling time c ref = 10f 2 ms external v ref input range 2.55 v dd v internal reference characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v dd = 3.3v.
ltc2356-12/ltc2356-14 4 2356fb power requirements the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 17) symbol parameter conditions min typ max units v dd supply voltage 3.1 3.3 3.6 v i dd supply current active mode nap mode sleep mode (ltc2356-12) sleep mode (ltc2356-14) l l 5.5 1.1 4 4 8 1.5 15 12 ma ma a a p d power dissipation active mode with sck in fixed state (hi or lo) 18 mw digital inputs and digital outputs the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v dd = 3.3v. symbol parameter conditions min typ max units v ih high level input voltage v dd = 3.6v l 2.4 v v il low level input voltage v dd = 3.1v l 0.6 v i in digital input current v in = 0v to v dd l 10 a c in digital input capacitance 5 pf v oh high level output voltage v dd = 3.3v, i out = C200a l 2.5 2.9 v v ol low level output voltage v dd = 3.1v, i out = 160a v dd = 3.1v, i out = 1.6ma l 0.05 0.10 0.4 v v i oz hi-z output leakage d out v out = 0v to v dd l 10 a c oz hi-z output capacitance d out 1 pf i source output short-circuit source current v out = 0v, v dd = 3.3v 20 ma i sink output short-circuit sink current v out = v dd = 3.3v 15 ma
ltc2356-12/ltc2356-14 5 2356fb timing characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: when these pins are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents greater than 100ma below gnd or greater than v dd without latchup. note 4: offset and full-gain specifcations are measured for a single-ended a in + input with a in C grounded and using the internal 2.5v reference. note 5: integral linearity is tested with an external 2.55v reference and is defned as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. the deviation is measured from the center of quantization band. note 6: guaranteed by design, not subject to test. note 7: recommended operating conditions. note 8: the analog input range is defned for the voltage difference between a in + and a in C . performance is specifed with a in C = 1.5v dc while driving a in + . note 9: the absolute voltage at a in + and a in C must be within this range. note 10: if less than 3ns is allowed, the output data will appear one clock cycle later. it is best for conv to rise half a clock before sck, when running the clock at rated speed. the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v dd = 3.3v. symbol parameter conditions min typ max units f sample(max) maximum sampling rate per channel (conversion rate) l 3.5 mhz t throughput minimum sampling period (conversion + acquisiton period) l 286 ns t sck clock period (note 16) l 15.872 10000 ns t conv conversion time (note 6) 16 18 sclk cycles t 1 minimum high or low sclk pulse width (note 6) 2 ns t 2 conv to sck setup time (notes 6, 10) 3 ns t 3 nearest sck edge before conv (note 6) 0 ns t 4 minimum high or low conv pulse width (note 6) 4 ns t 5 sck to sample mode (note 6) 4 ns t 6 conv to hold mode (notes 6, 11) 1.2 ns t 7 16th sck to conv interval (affects acquisition period) (notes 6, 7, 13) 45 ns t 8 delay from sck to valid data (notes 6, 12) 8 ns t 9 sck to hi-z at sdo (notes 6, 12) 6 ns t 10 previous sdo bit remains valid after sck (notes 6, 12) 2 ns t 12 v ref settling time after sleep-to-wake transition (note 14) 2 ms note 11: not the same as aperture delay. aperture delay is smaller (1ns) because the 2.2ns delay through the sample-and-hold is subtracted from the conv to hold mode delay. note 12: the rising edge of sck is guaranteed to catch the data coming out into a storage latch. note 13: the time period for acquiring the input signal is started by the 16th rising clock and it is ended by the rising edge of convert. note 14: the internal reference settles in 2ms after it wakes up from sleep mode with one or more cycles at sck and a 10f capacitive load. note 15: the full power bandwidth is the frequency where the output code swing drops to 3db with a 2.5v p-p input sine wave. note 16: maximum clock period guarantees analog performance during conversion. output data can be read with an arbitrarily long clock. note 17: v dd = 3.3v, f sample = 3.5msps. note 18: the ltc2356-14 is measured and specifed with 14-bit resolution (1lsb = 152v) and the ltc2356-12 is measured and specifed with 12-bit resolution (1lsb = 610v). note 19: the sampling capacitor at each input accounts for 4.1pf of the input capacitance.
ltc2356-12/ltc2356-14 6 2356fb typical performance characteristics sinad vs input frequency sfdr vs input frequency thd, 2nd and 3rd vs input frequency snr vs input frequency 1.4mhz sine wave 8192 point fft plot 100khz sine wave 8192 point fft plot frequency (mhz) 0.1 62 sinad (db) 65 68 71 74 1 10 100 2356 g01 59 56 53 50 77 frequency (mhz) 0.1 ?80 thd, 2nd, 3rd (db) ?74 ?68 ?62 ?56 1 10 100 2356 g02 ?86 ?92 ?98 ?104 ?50 thd 2nd 3rd frequency (mhz) 0.1 74 sfdr (db) 80 86 92 1 10 100 2356 g03 68 62 56 50 frequency (mhz) 0.1 62 snr (db) 65 68 71 74 1 10 100 2356 g04 59 56 53 50 77 frequency (hz) 0 magnitude (db) ?90 ?30 ?20 ?10 0 500k 1m 1.25m 2356 g05 ?110 ?50 ?70 ?100 ?40 ?120 ?60 ?80 250k 750k 1.5m 1.75m frequency (hz) 0 magnitude (db) ?90 ?30 ?20 ?10 0 500k 1m 1.25m 2356 g06 ?110 ?50 ?70 ?100 ?40 ?120 ?60 ?80 250k 750k 1.5m 1.75m t a = 25c, v dd = 3.3v (ltc2356-14)
ltc2356-12/ltc2356-14 7 2356fb 2356 g07 output code 0 ?1.0 differential linearity (lsb) ?0.8 ?0.4 ?0.2 0 1.0 0.4 4096 8192 ?0.6 0.6 0.8 0.2 12288 16384 output code 0 integral linearity (lsb) 0 1 2 16384 2356 g08 ?1 ?2 ?4 4096 8192 12288 ?3 4 3 conversion rate (msps) 2.0 sinad (db) 73 74 75 3.6 2356 g10 72 71 70 2.2 2.4 2.6 2.8 3 3.2 3.4 3.8 4.0 conversion rate (msps) 2.0 linearity (lsb) 3 4 2 1 0 ?1 ?2 ?3 ?4 3.6 2356 g09 2.4 2.8 3.2 4.0 3.4 2.2 2.6 3.0 3.8 max inl min inl max dnl min dnl frequency (hz) 1m 10m 100m 1g ?18 amplitude (db) ?12 ?6 0 2356 g11 ?24 ?30 ?36 6 12 frequency (hz) 100 cmrr (db) 0 ?20 ?40 ?60 ?80 ?100 ?120 1k 10k 100k 1m 2356 g12 10m 100m typical performance characteristics sinad vs conversion rate, input frequency = 1.4mhz differential and integral linearity vs conversion rate 2.5v p-p power bandwidth cmrr vs frequency differential linearity vs output code integral linearity vs output code t a = 25c, v dd = 3.3v (ltc2356-14)
ltc2356-12/ltc2356-14 8 2356fb conversion rate (mps) 0 0 v dd supply current (ma) 1 0.5 2 1.5 3 2.5 4 3.5 6 5.5 0.5 1 1.5 2 2356 g16 2.5 3.53 4 5 4.5 v dd (v) 2.4890 v ref (v) 2.4894 2.4898 2.4902 2.4892 2.4896 2.4900 2.8 3.0 3.2 3.4 2356 g15 2.6 3.6 frequency (hz) 1 10 ?50 psrr (db) ?45 ?40 ?35 ?30 100 1k 10k 100k 1m 2356 g13 ?55 ?60 ?65 ?70 ?25 load current (ma) 0.4 0.8 1.2 1.6 2356 g14 2.0 0.20 0.6 1.0 1.4 1.8 2.4890 v ref (v) 2.4894 2.4898 2.4902 2.4892 2.4896 2.4900 typical performance characteristics t a = 25c, v dd = 3.3v (ltc2356-12 and ltc2356-14) internal reference voltage vs load current internal reference voltage vs v dd v dd supply current vs conversion rate psrr vs frequency
ltc2356-12/ltc2356-14 9 2356fb 2356 bd ? + 1 2 7 3 4 s & h gnd exposed pad ltc2356-14 v ref 10f a in ? a in + 14-bit adc 3.3v10f 14 14-bit latch 8 10 9 three- state serial output port 2.5v reference timing logic v dd sdo conv sck 5 6 11 pin functions a in + (pin 1): noninverting analog input. a in + operates fully differentially with respect to a in C with a C1.25v to 1.25v differential swing with respect to a in C and a 0v to v dd common mode swing. a in C (pin 2): inverting analog input. a in C operates fully differentially with respect to a in + with a 1.25v to C1.25v differential swing with respect to a in + and a 0v to v dd common mode swing. v ref (pin 3): 2.5v internal reference. bypass to gnd and to a solid analog ground plane with a 10f ceramic capacitor (or 10f tantalum in parallel with 0.1f ceramic). can be overdriven by an external reference between 2.55v and v dd . gnd (pins 4, 5, 6, 11): ground and exposed pad. these ground pins and the exposed pad must be tied directly to the solid ground plane under the part. keep in mind that analog signal currents and digital output signal currents fow through these pins. v dd (pin 7): 3.3v positive supply. this single power pin supplies 3.3v to the entire device. bypass to gnd and to a solid analog ground plane with a 10f ceramic capacitor (or 10f tantalum in parallel with 0.1f ceramic). keep in mind that internal analog currents and digital output signal currents fow through this pin. care should be taken to place the 0.1f bypass capacitor as close to pins 6 and 7 as possible. sdo (pin 8): three-state serial data output. each set of output data words represents the difference between a in + and a in C analog inputs at the start of the previous conversion. the output format is 2s complement. sck (pin 9): external clock input. advances the conver - sion process and sequences the output data on the rising edge. responds to ttl (3.3v) and 3.3v cmos levels. one or more pulses wake from sleep. conv (pin 10): convert start. holds the analog input signal and starts the conversion on the rising edge. responds to ttl (3.3v) and 3.3v cmos levels. two conv pulses with sck in fxed high or fxed low state start nap mode. four or more conv pulses with sck in fxed high or fxed low state start sleep mode. block diagram
ltc2356-12/ltc2356-14 10 2356fb timing diagram nap mode and sleep mode waveforms sck to sdo delay ltc2356-12 timing diagram ltc2356-14 timing diagram sck conv internal s/h status sdo t 7 t 3 t 1 11817 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 t 2 t 6 t 8 t 4 t 5 t 8 t 9 t acq sample hold hold hi-z hi-z t conv 14-bit data word sdo represents the analog input from the previous conversion *bits marked "x" after d0 should be ignored. t throughput 2356 td01 d11 d10 d8 d7 d6 d5 d4 d3 d2 d1 d0 x* x* d9 sample 1 sck conv internal s/h status sdo t 7 t 3 t 1 11817 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 t 2 t 6 t 8 t 4 t 5 t 8 t 9 t acq sample hold hold hi-z hi-z t conv 14-bit data word sdo represents the analog input from the previous conversion t throughput 2356 td01b d13 d12 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d11 sample 1 sck conv nap sleep v ref t 1 t 12 t 1 note: nap and sleep are internal signals 2356 td02 t 8 t 10 sck sdo 2356 td03 v ih v oh v ol t 9 sck sdo v ih 90% 10%
ltc2356-12/ltc2356-14 11 2356fb driving the analog input the differential analog inputs of the ltc2356-12/ltc2356-14 may be driven differentially or as a single-ended input (i.e., the a in C input is set to v cm ). both differential analog inputs, a in + and a in C , are sampled at the same instant. any unwanted signal that is common to both inputs of each input pair will be reduced by the common mode rejec - tion of the sample-and-hold circuit. the inputs draw only one small current spike while charging the sample- and-hold capacitors at the end of conversion. during conversion, the analog inputs draw only a small leakage current. if the source impedance of the driving circuit is low, then the ltc2356-12/ltc2356-14 inputs can be driven directly. as source impedance increases, so will acquisition time. for minimum acquisition time with high source impedance, a buffer amplifer must be used. the main requirement is that the amplifer driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 39ns for full throughput rate). also keep in mind while choosing an input amplifer the amount of noise and harmonic distortion added by the amplifer. choosing an input amplifier choosing an input amplifer is easy if a few requirements are taken into consideration. first, to limit the magnitude of the voltage spike seen by the amplifer from charging the sampling capacitor, choose an amplifer that has a low output impedance (<100) at the closed-loop bandwidth frequency. for example, if an amplifer is used with a gain of 1 and has a unity-gain bandwidth of 50mhz, then the output impedance at 50mhz must be less than 100. the second requirement is that the closed-loop bandwidth must be greater than 40mhz to ensure adequate small-signal settling for full throughput rate. if slower op amps are used, more time for settling can be provided by increasing the time between conversions. the best choice for an op amp to drive the ltc2356-12/ ltc2356-14 will depend on the application. generally, ap - plications fall into two categories: ac applications where dynamic specifcations are most critical and time domain applications where dc accuracy and settling time are most critical. the following list is a summary of the op amps that are suitable for driving the ltc2356-12/ltc2356-14. (more applications information detailed information is available in the linear technology databooks and our website at www.linear.com.) ltc1566-1: low noise 2.3mhz continuous time low- pass filter. lt ? 1630: dual 30mhz rail-to-rail voltage fb amplifer. 2.7v to 15v supplies. very high a vol , 500v offset and 520ns settling to 0.5lsb for a 4v swing. thd and noise are C93db to 40khz and below 1lsb to 320khz (a v = 1, 2v p-p into 1k, v s = 5v), making the part excellent for ac applications (to 1/3 nyquist) where rail-to-rail perfor - mance is desired. quad version is available as lt1631. lt1632: dual 45mhz rail-to-rail voltage fb amplifer. 2.7v to 15v supplies. very high a vol , 1.5mv offset and 400ns settling to 0.5lsb for a 4v swing. it is suitable for applications with a single 5v supply. thd and noise are C93db to 40khz and below 1lsb to 800khz (a v = 1, 2v p-p into 1k, v s = 5v), making the part excellent for ac applications where rail-to-rail performance is desired. quad version is available as lt1633. lt1813: dual 100mhz 750v/s 3ma voltage feedback amplifer. 5v to 5v supplies. distortion is C86db to 100khz and C77db to 1mhz with 5v supplies (2v p-p into 500). excellent part for fast ac applications with 5v supplies. lt1801: 80mhz gbwp, C75dbc at 500khz, 2ma/amplifer, 8.5nv/ hz. lt1806/lt1807: 325mhz gbwp, C80dbc distortion at 5mhz, unity-gain stable, r-r in and out, 10ma/ampli - fer, 3.5nv/ hz. lt1810: 180mhz gbwp, C90dbc distortion at 5mhz, unity- gain stable, r-r in and out, 15ma/amplifer, 16nv/ hz. lt1818/lt1819: 400mhz, 2500v/s,9ma, single/dual voltage mode operational amplifer. lt6200: 165mhz gbwp, C85dbc distortion at 1mhz, unity-gain stable, r-r in and out, 15ma/amplifier, 0.95nv/ hz. lt6203: 100mhz gbwp, C80dbc distortion at 1mhz, unity-gain stable, r-r in and out, 3ma/amplifier, 1.9nv/ hz. lt6600-10: amplifer/filter differential in/out with 10mhz cutoff.
ltc2356-12/ltc2356-14 12 2356fb gnd ltc2356-12/ ltc2356-14 lt1790-3 v ref 10f 3.5v to 18v 11 3 3v 2356 f03 + a in + c4 10f 2356 f02 r2 1.6k c2 1f c1 1f c1, c2: film type c3: cog type c4: ceramic bypass r1 1.6k 1 2 3 ltc2356-12/ ltc2356-14 a in ? v ref r3 51 c3 56pf v in 10f v cm 1.5v dc 11 3 a in ? ltc2356-12/ ltc2356-14 a in + 47pf 2 1 51 gnd v ref 2356 f01 applications information input filtering and source impedance the noise and the distortion of the input amplifer and other circuitry must be considered since they will add to the ltc2356-12/ltc2356-14 noise and distortion. the small-signal bandwidth of the sample-and-hold circuit is 50mhz. any noise or distortion products that are pres - ent at the analog inputs will be summed over this entire bandwidth. noisy input circuitry should be fltered prior to the analog inputs to minimize noise. a simple 1-pole rc flter is suffcient for many applications. for example, figure 1 shows a 47pf capacitor from a in + to ground and a 51 source resistor to limit the input bandwidth to 47mhz. the 47pf capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the adc input from sampling-glitch sensitive circuitry. high quality capacitors and resistors should be used since these components can add distortion. npo and silvermica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal flm surface mount resistors are much less susceptible to both problems. when high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole flter is required. high external source resistance, combined with the 13pf of input capacitance, will reduce the rated 50mhz bandwidth and increase acquisition time beyond 39ns. figure 1. rc input filter inverting input. the 1.25v range is also ideally suited for ac-coupled signals in single supply applications. figure 2 shows how to ac couple signals in a single supply system without needing a mid-supply 1.5v external reference. the dc common mode level is supplied by the previous stage that is already bounded by the single supply voltage of the system. the common mode range of the inputs extend from ground to the supply voltage v dd . if the difference between the a in + and a in C inputs exceeds 1.25v, the output code will stay fxed at zero and all ones and if this difference goes below C1.25v, the output code will stay fxed at one and all zeros. figure 2. ac coupling of ac signals with 1khz low cutoff frequency input range the analog inputs of the ltc2356-12/ltc2356-14 may be driven fully differentially with a single supply. each input may swing up to 2.5v p-p individually. when using the internal reference, the non-inverting input should never be more than 1.25v more positive or more negative than the internal reference the ltc2356-12/ltc2356-14 has an on-chip, temperature compensated, bandgap reference that is factory trimmed to 2.5v to obtain a bipolar 1.25v input span. the refer - ence amplifer output v ref , (pin 3) must be bypassed with a capacitor to ground. the reference amplifer is stable with capacitors of 1f or greater. for the best noise performance, a 10f ceramic or a 10f tantalum in paral - lel with a 0.1f ceramic is recommended. the v ref pin can be overdriven with an external reference as shown in figure 3. overdriving v ref pin with an external reference
ltc2356-12/ltc2356-14 13 2356fb a in ? ltc2356-14 a in + c1 47pf to 1000pf 1 r1 51 c3 1f c5 0.1f 5v ?5v c4 1f r5 1k 1.5v cm r3 499 r4 499 r6 1k c2 47pf to 1000pf r2 51 c6 0.1f v in 1.25v p-p max 2356 f06a ? + u1 1/2 lt1819 ? + u2 1/2 lt1819 input voltage (v) 2?s complement output code 2356 f05 011...111 011...110 011...101 100...000 100...001 100...010 fs ? 1lsb ?fs frequency (hz) 100 cmrr (db) 0 ?20 ?40 ?60 ?80 ?100 ?120 1k 10k 100k 1m 2356 f04 10m 100m applications information figure 3. the voltage of the external reference must be higher than the 2.5v output of the internal reference. the recommended range for an external reference is 2.55v to v dd . an external reference at 2.55v will see a dc quiescent load of 0.75ma and as much as 3ma during conversion. input span versus reference voltage the differential input range has a bipolar v ref /2 voltage span that equals the difference between the voltage at the reference buffer output v ref at pin 3, and the voltage at the ground (exposed pad ground). the differential input range of the adc is 1.25v when using the internal reference. the internal adc is referenced to these two nodes. this relationship also holds true with an external reference. differential inputs the ltc2356-12/ltc2356-14 have a unique differential sample-and-hold circuit that measures input voltages from ground to v dd . the adc will always convert the bipolar difference of a in + C a in C , independent of the common mode voltage at the inputs. the common mode rejection holds up at extremely high frequencies, see figure 4. the only requirement is that both inputs not go below ground or exceed v dd . integral nonlinearity errors (inl) and dif - ferential nonlinearity errors (dnl) are largely independent of the common mode voltage. however, the offset error will vary. the change in offset error is typically less than 0.1% of the common mode voltage. figure 5 shows the ideal input/output characteristics for the ltc2356-12/ltc2356-14. the code transitions occur midway between successive integer lsb values (i.e., 0.5lsb, 1.5lsb, 2.5lsb, fs C 1.5lsb). the output code is 2s complement with 1lsb = 2.5v/16384 = 153v for the ltc2356-14, and 1lsb = 2.5v/4096 = 610v for the ltc2356-12. the ltc2356-14 has 1lsb rms of random white noise. figure 6a shows the ltc1819 converting a single ended input signal to differential input signals for optimum thd and sfdr performance as shown in the fft plot (figure 6b). figure 4. cmrr vs frequency figure 5. ltc2356-12/ltc2356-14 transfer characteristic figure 6a. the lt1819 driving the ltc2356-14 differentially
ltc2356-12/ltc2356-14 14 2356fb v ref bypass 0805 size v dd bypass 0805 size 2356 f07 optional input filtering frequency (hz) magnitude (db) ?60 ?30 ?20 2356 f06b ?70 ?80 ?120 ?100 0 ?10 ?40 ?50 ?90 ?110 0 371k 185k 556k 741k applications information board layout and bypassing wire wrap boards are not recommended for high resolu - tion and/or high speed a/d converters. to obtain the best performance from the ltc2356-12/ltc2356-14, a printed circuit board with ground plane is required. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track. if optimum phase match between the inputs is desired, the length of the two input wires should be kept matched. high quality tantalum and ceramic bypass capacitors should be used at the v dd and v ref pins as shown in the block diagram on the frst page of this data sheet. for optimum performance, a 10f surface mount tantalum capacitor with a 0.1f ceramic is recommended for the v dd and v ref pins. alternatively, 10f ceramic chip capacitors such as murata grm219r60j106m may be used. the capacitors must be located as close to the pins as possible. the traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. figure 7 shows the recommended system ground connec - tions. all analog circuitry grounds should be terminated at the ltc2356-12/ltc2356-14 gnd (pins 4, 5, 6 and exposed pad). the ground return from the ltc2356- 12/ltc2356-14 (pins 4, 5, 6 and exposed pad) to the power supply should be low impedance for noise free operation. in applications where the adc data outputs and control signals are connected to a continuously ac- tive microprocessor bus, it is possible to get errors in the conversion results. these errors are due to feedthrough from the microprocessor to the successive approximation comparator. the problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the adc data bus. power-down modes upon power-up, the ltc2356-12/ltc2356-14 is initial - ized to the active state and is ready for conversion. the nap and sleep mode waveforms show the power-down modes for the ltc2356-12/ltc2356-14. the sck and conv inputs control the power-down modes (see timing diagrams). two rising edges at conv, without any interven - ing rising edges at sck, put the ltc2356-12/ltc2356-14 in nap mode and the power consumption drops from 18mw to 4mw. the internal reference remains powered in nap mode. one or more rising edges at sck wake up the ltc2356-12/ltc2356-14 very quickly, and conv can start an accurate conversion within a clock cycle. four rising edges at conv, without any intervening rising edges at sck, put the ltc2356-12/ltc2356-14 in sleep mode and the power consumption drops from 18mw to 13w. one or more rising edges at sck wake up the ltc2356 - 12/ltc2356-14 for operation. the internal refer - ence (v ref ) takes 2ms to slew and settle with a 10f load. figure 7. recommended layout figure 6b. ltc2356-12 6mhz sine wave 4096 point fft plot with the lt1819 driving the inputs differentially
ltc2356-12/ltc2356-14 15 2356fb applications information note that, using sleep mode more frequently than every 2ms, compromises the settled accuracy of the internal reference. note that, for slower conversion rates, the nap and sleep modes can be used for substantial reductions in power consumption. digital interface the ltc2356-12/ltc2356-14 has a 3-wire spi-compatible (serial protocol interface) interface. the sck and conv inputs and sdo output implement this interface. the sck and conv inputs accept swings from 3.3v logic and are ttl compatible, if the logic swing does not exceed v dd . a detailed description of the three serial port signals follows. conversion start input (conv) the rising edge of conv starts a conversion, but subse - quent rising edges at conv are ignored by the ltc2356 - 12/ ltc2356-14 until the following 16 sck rising edges have occurred. it is necessary to have a minimum of 16 rising edges of the clock input sck between rising edges of conv. but to obtain maximum conversion speed (with a 63mhz sck), it is necessary to allow two more clock periods between conversions to allow 39ns of acquisition time for the internal adc sample-and-hold circuit. with 16 clock periods per conversion, the maximum conversion rate is limited to 3.5msps to allow 39ns for acquisition time. in either case, the output data stream comes out within the frst 16 clock periods to ensure compatibility with processor serial ports. the duty cycle of conv can be arbitrarily chosen to be used as a frame sync signal for the processor serial port. a simple approach to generate conv is to create a pulse that is one sck wide to drive the ltc2356-12/ltc2356-14 and then buffer this signal with the appropriate number of inverters to ensure the cor - rect delay driving the frame sync input of the processor serial port. it is good practice to drive the ltc2356-12/ ltc2356-14 conv input frst to avoid digital noise inter - ference during the sample-to-hold transition triggered by conv at the start of conversion. it is also good practice to keep the width of the low portion of the conv signal greater than 15ns to avoid introducing glitches in the front end of the adc just before the sample-and-hold goes into hold mode at the rising edge of conv. minimizing jitter on the conv input in high speed applications where high amplitude sine waves above 100khz are sampled, the conv signal must have as little jitter as possible (10ps or less). the square wave output of a common crystal clock module usually meets this requirement . the challenge is to generate a conv signal from this crystal clock without jitter corruption from other digital circuits in the system. a clock divider and any gates in the signal path from the crystal clock to the conv input should not share the same integrated circuit with other parts of the system. as shown in figure 8, the sck and conv inputs should be driven frst, with digital buffers used to drive the serial port interface. also note that the master clock in the dsp may already be corrupted with jitter, even if it comes directly from the dsp crystal. another problem with high speed processor clocks is that they often use a low cost, low speed crystal (i.e., 10mhz) to generate a fast, but jittery, phase-locked-loop system clock (i.e., 40mhz). the jitter in these pll-generated high speed clocks can be several nanoseconds. note that if you choose to use the frame sync signal generated by the dsp port, this signal will have the same jitter of the dsps master clock. the typical application figure on page 16 shows a cir - cuit for level-shifting and squaring the output from an rf signal generator or other low-jitter source. a single d-type fip fop is used to generate the conv signal to the ltc2356-12/ltc2356-14. re-timing the master clock signal eliminates clock jitter introduced by the controlling device (dsp, fpga, etc.) both the inverter and fip fop must be treated as analog components and should be powered from a clean analog supply. serial clock input (sck) the rising edge of sck advances the conversion process and also udpates each bit in the sdo data stream. after conv rises, the third rising edge of sck starts clocking out the 12/14 data bits with the msb sent frst. a simple approach is to generate sck to drive the ltc2356-12/ ltc2356-14 frst and then buffer this signal with the appropriate number of inverters to drive the serial clock input of the processor serial port. use the falling edge of the clock to latch data from the serial data output (sdo)
ltc2356-12/ltc2356-14 16 2356fb package description into your processor serial port. the 14-bit serial data will be received right justifed, in a 16-bit word with 16 or more clocks per frame sync. it is good practice to drive the ltc2356-12/ltc2356-14 sck input frst to avoid digi - tal noise interference during the internal bit comparison decision by the internal high speed comparator. unlike the conv input, the sck input is not sensitive to jitter because the input signal is already sampled and held constant. serial data output (sdo) upon power-up, the sdo output is automatically reset to the high impedance state. the sdo output remains in high impedance until a new conversion is started. sdo sends out 12/14 bits in 2s complement format in the output data stream beginning at the third rising edge of sck after the rising edge of conv. sdo is always in high impedance mode when it is not sending out data bits. please note the delay specifcation from sck to a valid sdo. sdo is always guaranteed to be valid by the next rising edge of sck. the 16-bit output data stream is compatible with the 16-bit or 32-bit serial port of most processors. loading on the sdo line must be minimized. sdo can directly drive most fast cmos logic inputs directly. how - ever, the general purpose i/o pins on many programmable logic devices (fpgas, cplds) and dsps have excessive capacitance. in these cases, a 100 resistor in series with sdo can isolate the input capacitance of the receiv - ing device. if the receiving device has more than 10pf of input capacitance or is located far from the ltc2356- 12/ltc2356-14, an nc7svu04p5x inverter can be used to provide more drive. applications information 10 1 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.53 0.152 (.021 .006) 0.18 (.007) 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 1.68 0.102 (.066 .004) 1.88 0.102 (.074 .004) 0.50 (.0197) bsc 0.305 0.038 (.0120 .0015) typ bottom view of exposed pad option 1.68 (.066) 1.88 (.074) 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) msop (mse) 0911 rev h seating plane 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 0.1016 0.0508 (.004 .002) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.05 ref 0.29 ref mse package 10-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1664 rev h) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc2356-12/ltc2356-14 17 2356fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 01/10 revise values in pin confguration section 2 b 06/12 changed straight binary to 2s complement 13
ltc2356-12/ltc2356-14 18 2356fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2006 lt 0612 rev b ? printed in usa pre v cc 1k 1k 50 v cc nl17sz74 convert enable nc7svu04p5x master clock 0.1f conv ltc2356 control logic (fpga, cpld, dsp, etc.) d q q conv sck sdo 100 nc7svu04p5x clr 2356 ta03 part number description comments adcs ltc1402 12-bit, 2.2msps serial adc 5v or 5v supply, 4.096v or 2.048v span ltc1403/ltc1403a 12-/14-bit, 2.8msps serial adc 3v, 14mw, unipolar inputs, msop package ltc1403-1/ltc1403a-1 12-/14-bit, 2.8msps serial adc 3v, 14mw, bipolar inputs, msop package ltc1405 12-bit, 5msps parallel adc 5v, selectable spans, 115mw ltc1407/ltc1407a 12-/14-bit, 3msps simultaneous sampling adc 3v, 2-channel differential, unipolar inputs, 14mw, msop package ltc1407-1/ltc1407a-1 12-/14-bit, 3msps simultaneous sampling adc 3v, 2-channel differential, bipolar inputs, 14mw, msop package ltc1411 14-bit, 2.5msps parallel adc 5v, selectable spans, 80db sinad ltc1412 12-bit, 3msps parallel adc 5v supply, 2.5v span, 72db sinad lct1414 14-bit, 2.2msps parallel adc 5v supply, 2.5v span, 78db sinad ltc1420 12-bit, 10msps parallel adc 5v, selectable spans, 71db sinad ltc1604 16-bit, 333ksps parallel adc 5v supply, 2.5v span, 90db sinad ltc1608 16-bit, 500ksps parallel adc 5v supply, 2.5v span, 90db sinad ltc1609 16-bit, 200ksps serial adc 5v, confgurable bipolar/unipolar inputs ltc1864/ltc1865 16-bit, 250ksps serial adcs 5v supply, 1 and 2 channel, 4.3mw, msop package ltc2355-12/ltc2355-14 12-/14-bit, 3.5msps serial adc 3.3v 14mw, 0v to 2.5v span, msop package dacs ltc1666/ltc1667/ltc1668 12-/14-/16-bit, 50msps dacs 87db sfdr, 20ns settling time ltc1592 16-bit, serial softspan? i out dac 1lsb inl/dnl, software selectable spans references lt1790-2.5 micropower series reference in sot-23 0.05% initial accuracy, 10ppm drift lt1461-2.5 precision voltage reference 0.04% initial accuracy, 3ppm drift lt1460-2.5 micropower series voltage reference 0.075% initial accuracy, 10ppm drift low-jitter clock timing with rf sine generator using clock squaring/level shifting circuit and re-timing flip-flop related parts typical application

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